Circuit designers use electronic design automation (EDA) tools, a category of computer aided design (CAD) tools, to design and lay out electronic circuits, including simulating the operation of the circuit, determining where cells (i.e., logic elements including devices, e.g., transistors) should be placed and where the interconnects that couple the cells together should be routed. EDA tools allow designers to construct a circuit and simulate its performance using a computer and without requiring the costly and lengthy process of fabrication. EDA tools are indispensable for designing modern ICs, particularly very-large-scale integrated circuits (VSLICs). For this reason, EDA tools are in wide use.
One such EDA tool performs timing signoff. Timing signoff is one of the last steps in the IC design process and ensures that signal propagation speed (i.e., delay) in a newly-designed circuit is such that the circuit will operate as intended. Signals that propagate too slowly through the circuit cause setup violations; signals that propagate too quickly through the circuit cause hold violations. Setup or hold violations frustrate the logic of the circuit and prevent it from performing the job it was designed to do.
Timing signoff is performed with highly accurate models of the circuit under multiple sets of assumptions regarding expected variations, called “corners.” Process-voltage-temperature (PVT) corners are based on assumptions regarding variations in device operation from one IC to another, supply voltage and operating temperature. Resistance-capacitance (R, C, or RC) corners are based on assumptions regarding variations in one or both of interconnect resistance and capacitance from one IC to another. Conventional timing signoff identifies setup and hold violations in a “slow” PVT corner (in which process variations are assumed to yield relatively slow-switching devices and supply voltage and operating temperature are such that device switching speed are their slowest) and a “worst” RC corner (in which process variations are assumed to yield interconnects having relatively high resistance and capacitance). Conventional timing signoff also identifies hold violations in a “fast” PVT corner (in which process variations are assumed to yield relatively fast-switching devices and supply voltage and operating temperature are such that device switching speeds are their fastest) and a “best” RC corner (in which process variations are assumed to yield interconnects having relatively low resistance and capacitance). Conventional signoff timing also takes on-chip variations (OCV), which are process variations occurring over the area of a given IC, into account using statistical methods.
Conserving resources, including energy, has become a pre-eminent objective in today's world. Manufacturers of ICs are sensitive to the need to improve the energy efficiency of their products. Adaptive voltage and scaling optimization (AVSO) is an important component of that overall strategy. The objective underlying AVSO is that an IC should be powered at the lowest possible voltage without sacrificing performance. ICs employing AVSO (“AVSO ICs”) determine signal propagation speed in real time and adjust supply voltage to ensure that signal propagation speed remains such that the IC will operate as intended. AVSO has demonstrated its ability to conserve energy and therefore is expected to be evermore widely used in future ICs.